1. Field of the Invention
The invention relates to a technique for conserving power in computer systems, and more particularly, to circuitry that responds to certain special bus cycles by placing cache memory devices in the computer system into low power mode.
2. Description of the Related Art
Rapid improvements in integrated circuit components have led to more powerful computer systems. The first generation of IC components was built using bipolar technology. However, bipolar devices dissipated large amounts of power, which proved to be an obstacle to manufacturing larger and denser components. Next, IC components were manufactured with metal-oxide-silicon (MOS) technology. But it was not until the development of complementary metal-oxide-silicon (CMOS) devices before the IC industry began its rapid growth. CMOS components dissipate relatively low power when they are not in active operation. As a result, the transition to CMOS technology has enabled the manufacture of denser and more powerful IC components, while maintaining relatively low power consumption.
However, even with the use of CMOS technology, power dissipation by the computer system components still causes significant amounts of energy to be wasted, particularly when the computer system is powered on but not in use. Heretofore, efforts have concentrated on stopping or slowing down the clock to the main microprocessor and turning off peripheral devices such as disk drives, video systems and I/O ports to conserve power. Such an apparatus for reducing computer system power consumption is described in U.S. Pat. No. 4,980,836, entitled "Apparatus for Reducing Computer System Power Consumption," by Carter, et al. Carter describes a computer system that monitors its address bus to determine when selected peripheral devices have not been accessed for a preset amount of time. When the preset amount of time has expired, the computer system powers itself down and stops the system clock. In addition, the keyboard electronics are placed into low power mode and power is removed from various miscellaneous logic. However, the memory devices remained powered up to retain programs. Later advances allowed powering off even the memory devices by storing the entire system state to hard disk before completely powering down. But this is a final step and power conservation is desired at all levels and periods, not just after very long periods.
As microprocessor clock speeds have rapidly increased, the gap between the microprocessor cycle time and the access time for a memory has also increased. Mainly due to cost reasons, computer manufacturers implement main memory systems with dynamic random access memories (DRAMs). DRAM access times have been unable to keep pace with microprocessor cycle times, which requires that wait states be inserted any time data has to by transferred between the microprocessor and main memory. To improve performance, cache memory systems are implemented between the microprocessor and the main memory. Cache memory systems are usually implemented with fast SRAMs, which allow data to be accessed by microprocessors without the need for wait states. Cache memory stores blocks of data retrieved from main memory. Thus, any access to the cache memory that results in a hit would save considerable amounts of time. A cache miss will still require data to be retrieved from main memory.
Because of the very high speeds of the devices, cache memory systems consume significant amounts of power. As the size of cache memory systems increases, the power consumption also increases. This has been a large area of power consumption in high performance computer systems, but energy savings are desired in even these high performance systems. As a result, it is desirable that the power dissipation of these cache devices be reduced whenever possible to aid in the overall reduction of power being consumed.